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include
qore
macros-ia64.h
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/* -*- mode: c++; indent-tabs-mode: nil -*- */
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/*
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macros-itanium.h
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assembly macros for the Itanium (IA-64) architecture
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Qore Programming Language
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Copyright 2003 - 2013 David Nichols
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _QORE_MACHINE_MACROS_H
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#define _QORE_MACHINE_MACROS_H
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#define STACK_DIRECTION_DOWN 1
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#ifdef __GNUC__
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#ifdef __LP64__
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#define HAVE_ATOMIC_MACROS
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#define HAVE_CHECK_STACK_POS
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// 64-bit IA-64 atomic operations borrowed from linux
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#define ia64_cmpxchg4_acq(ptr, new, old) ({ \
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unsigned long ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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(int)ia64_intri_res; \
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})
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static
__inline__
int
ia64_atomic_add (
int
i,
volatile
int
*v) {
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int
old, vnew;
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do
{
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old = *v;
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vnew = old + i;
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}
while
(ia64_cmpxchg4_acq(v, vnew, old) != old);
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return
vnew;
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}
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static
__inline__
int
ia64_atomic_sub (
int
i,
volatile
int
*v) {
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int
old, vnew;
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do
{
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old = *v;
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vnew = old - i;
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}
while
(ia64_cmpxchg4_acq(v, vnew, old) != old);
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return
vnew;
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}
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static
inline
void
atomic_inc(
volatile
int
*a) {
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ia64_atomic_add(1, a);
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}
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// returns 1 when counter reaches zero, 0 if not
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static
inline
int
atomic_dec(
volatile
int
*a) {
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return
!ia64_atomic_sub(1, a);
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}
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static
inline
size_t
get_stack_pos() {
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size_t
addr;
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asm
volatile
(
"mov %0=sp"
:
"=r"
(addr));
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return
addr;
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}
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static
inline
size_t
get_rse_bsp() {
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size_t
addr;
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asm
volatile
(
"mov %0=ar.bsp"
:
"=r"
(addr));
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return
addr;
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}
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#endif // #ifdef __LP64__
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#endif // #ifdef __GNUC__
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#ifdef __HP_aCC
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#ifdef __LP64__
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#define HAVE_ATOMIC_MACROS
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#define HAVE_CHECK_STACK_POS
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// these routines are implemented in assembler
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extern
"C"
void
atomic_inc(
int
*v);
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extern
"C"
int
atomic_dec(
int
*v);
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extern
"C"
size_t
get_stack_pos();
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extern
"C"
size_t
get_rse_bsp();
// get ia64 Register Stack Engine backing store pointer
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#endif // #ifdef __LP64__
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#endif // #ifdef __HP_aCC
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#endif // #ifndef _QORE_MACHINE_MACROS_H
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